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fedl610q101-01 issue date: jan. 23, 2013 ml610q101/ML610Q102 8-bit microcontroller 1/21 general description this lsi is a high-performance 8-bit cmos microcontroller into which rich peripheral circuits, such as timers, pwm, uart, voltage level supervisor (vls) function, and 10-bit successive a pproximation type a/d converter, are incorporated around 8-bit cpu nx-u8/100. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture parallel processing. the on-chip debug function that is installed enables program debugging and programming. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system: 16-bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on-chip debug function ? minimum instruction execution time 30.5 s (@32.768khz system clock) 0.122 s (@8.192mhz system clock) ? internal memory ? ml610q101 : internal 4kbyte flash rom (2k 16 bits) (including unusable 32 byte test data area) ? ML610Q102 : internal 6kbyte flash rom (3k 16 bits) (including unusable 32 byte test data area) ? internal 256byte data ram (256 8 bits) ? interrupt controller ? 1 non-maskable interrupt source (internal source: 1) ? 21 maskable interrupt sources (internal sources: 16, external sources: 5) ? time base counter (tbc) ? low-speed time base counter 1 channel ? high-speed time base counter 1 channel ? watchdog timer (wdt) ? non-maskable interrupt and reset ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) ? timer ? 8 bits 6 channels (16-bit configuration available) ? support continuos timer mode/one shot timer mode ? timer start/stop function by software or external trigger input
fedl610q101 -01 ml610q101/ML610Q102 2/21 ? pwm ? resolution 16 bits 1 channel ? support continuos timer mode/one shot timer mode ? pwm start/stop function by software or external trigger input ? uart ? half-duplex ? txd/rxd 1 channels ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? successive approximation type a/d converter (sa-adc) ? 10-bit a/d converter ? input 6 channels ? analog comparator ? operating voltage: v dd = 2.7v to 5.5v ? input voltage by common mode: v dd = 0.1v to v dd - 1.5v ? hysteresis (comparator0 only): 20mv(typ.) ? allows selection of interrupt disabled mode,falling-edge interrupt mode,rising-edge interrupt mode, or both-edge interrupt mode. ? general-purpose ports (gpio) ? input/output port 11 channels (including secondary functions) ? reset ? reset by the reset_n pin ? reset by power-on detection ? reset by the watchdog timer (wdt) overflow ? reset by voltage level supervisor(vls) ? voltage level supervisor(vls) ? judgment accuracy: 3.0% (typ.) ? it can be used for low level detection reset. ? clock ? low-speed clock: built-in rc oscillation (32.768 khz) ? high-speed clock: built-in pll oscillation (16.384 mhz), external clock the clock of the cpu is 8.192mhz(max) ? selection of high-speed clock mode by software: built-in pll oscillation, external clock ? power management ? halt mode: instruction execution by cpu is suspended (peripheral circuits are in operating states). ? stop mode: stop of low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) ? block control function: power down (reset registers and stop clock supply) the circuits of unused peripherals.
fedl610q101 -01 ml610q101/ML610Q102 3/21 ? shipment ? 16-pin plastic ssop ml610q101-xxxmb (blank product: ml610q101-nnnmb) ML610Q102-xxxmb (blank product: ML610Q102-nnnmb) ? guaranteed operating range ? operating temperature: ? 40 c to 85 c ? operating voltage: v dd = 2.7v to 5.5v
fedl610q101 -01 ml610q101/ML610Q102 4/21 block diagram ml610q101 block diagram figure 1 show the block diagram of the ml610q101. "*" indicates secondary function, tertiary function or quaternary function of each port. figure 1 ml610q101 block diagram program memory (flash) 4kbyte uart rxd0 txd0* int 1 ram 256byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 6 8bit timer 6 int 1 pwm gpio pa0 to pa2 int 5 pb0 to pb7 data-bus pwmc* test reset_n osc power reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss analog comparator 2 cmp0p* cmp0m* int 2 10bit-adc ain0* to ain5* int 1 vls 1 cmp1out* cmp1p* cmp0pout* cmp0nout* int 1
fedl610q101 -01 ml610q101/ML610Q102 5/21 ML610Q102 block diagram figure 2 show the block diagram of the ML610Q102. "*" indicates secondary function, tertiary function or quaternary function of each port. figure 2 ML610Q102 block diagram program memory (flash) 6kbyte uart rxd0 txd0* int 1 ram 256byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 6 8bit timer 6 int 1 pwm gpio pa0 to pa2 int 5 pb0 to pb7 data-bus pwmc* test reset_n osc power reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss analog comparator 2 cmp0p* cmp0m* int 2 10bit-adc ain0* to ain5* int 1 vls cmp0out* cmp1out* cmp1p* cmp0pout* cmp0nout* int 1
fedl610q101 -01 ml610q101/ML610Q102 6/21 pin configuration ml610q101/ML610Q102 ssop16 pin layout figure 3 show the ssop16 pin layout of the ml610q101/ML610Q102. figure 3 ml610q101/ML610Q102 ssop16 pin configuration reset_n test pb0 / pwmc / outclk / cmp1out pb1 / txd0 pb2 / cmp0pout pb3 / cmp0mout pa2 / clki n / cmp0out v pp 1 2 3 4 5 6 7 8 pa0 / pwmc / outclk / tm9out pb7 / lsclk / pwmc v dd v ss pb6 / clkin pb5 / pb4 / txd0 pa1 / lsclk / tmfout 16 15 14 13 12 11 10 9
fedl610q101 -01 ml610q101/ML610Q102 7/21 list of pins primary function secondary function tertiary function quaternary function pin no. pin name i/o function pin name i/o function pin name i/o function pin name i/o function 1 reset_n i reset input pin ? ? ? ? ? ? ? ? ? 2 test i/o input/output pin for testing ? ? ? ? ? ? ? ? ? 3 pb0/ exi4/ ain2/ rxd0 i/o input/output port, external interrupt 4, adc input 2, uart receive pwmc o pwmc output outclk o high-speed clock output cmp1o ut o cmp1 output 4 pb1/ exi5/ ain3 i/o input/output port, external interrupt 5,adc input 3 ? ? ? txd0 o uart data output ? ? ? 5 pb2 i/o input/output port, ? ? ? ? ? ? cmp0p out o cmp0 h; n output 6 pb3 i/o input/output port ? ? ? ? ? ? cmp0n out o cmp0 h; n output 7 pa2/exi2 i/o input/output port, external interrupt ? ? ? clkin i clock input cmp0o ut o cmp0 output 8 v pp ? power supply pin for flash rom ? ? ? ? ? ? ? ? ? 9 pa1/ exi1/ ain1/ cmp1p i/o input port, external interrupt 1, adc input 1, comparator1 non-inverting input ? ? ? lsclk o low speed clock output tmf out o timer f output 10 pb4/ cmp0p i/o input/output port, comparator0 non-inverting input ? ? ? txd0 o uart data output ? ? ? 11 pb5/ rxd0/ cmp0m i/o input/output port, uart data receive, comparator1 inverting input ? ? ? ? ? ? ? ? ? 12 pb6/ ain4 i/o input/output port, adc input 4 clkin i clock input ? ? ? ? ? ? 13 vss ? negative power supply pin ? ? ? ? ? ? ? ? ? 14 v dd ? positive power supply pin ? ? ? ? ? ? ? ? ? 15 pb7/ ain5 i/o input/output port, adc input 5 lsclk o low-speed clock output ? ? ? pwmc o pwmc output 16 pa0/ exi0/ ain0 i/o input port, external interrupt 0, adc input 0 pwmc o pwmc output outclk o high-speed clock output tm9ou t o timer 9 output
fedl610q101 -01 ml610q101/ML610Q102 8/21 pin description pin name i/o description primary/ secondary/ tertiary/ quaternary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative clkin i high-speed clock output pin. this pin is used as the tertiary function of the pa2 or the secondary function of pb6 pin. secondary/ tertiary ? lsclk o low-speed clock output pin. this pin is used as the tertiary function of the pa1 or the secondary function of the pb7 pin. secondary/ tertiary ? outclk o high-speed clock output pin. this pin is used as the tertiary function of the pa0 or pb0 pin. tertiary ? general-purpose input/output port pa0 to pa2 pb0 to pb7 i/o general-purpose input/output port. since these pins have secondary functions and tertiary functions and quaternary functions, the pins cannot be used as a port when the secondary functions and tertiary functions and quaternary functions are used. primary positive uart txd0 o uart0 data output pin. this pin is used as the tertiary function of the pb1 or pb4 pin. tertiary positive rxd0 i uart0 data input pin. this pin is used as the primary function of the pb0 or pb5 or the quaternary function of the pb7 pin. primary positive pwm pwmc o pwmc output pin. this pin is used as the secondary function of the pb0 or pa0 or the quaternary function of the pb7 pin. secondary quaternary positive external interrupt exi0 to 2 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the pa0 ? pa2 pins. primary positive/ negative exi4,5 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the pb0, pb1 pins. primary positive/ negative timer tntg i external clock input pin used for both timer e and timer f.these pins are used as the primary function of the pa0-pa2, pb0-pb7 pins. primary ? tm9out o timer 9 output pin. this pin is used as the quat ernary function of the pa0 pin. quaternary positive tmfout o timer f output pin. this pin is used as the quat ernary function of the pa1 pin. quaternary positive
fedl610q101 -01 ml610q101/ML610Q102 9/21 pin name i/o description primary/ secondary/ tertiary/ quaternary logic successive approximation type a/d converter ain0 i channel 0 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pa0 pin. primary ? ain1 i channel 1 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pa1 pin. primary ? ain2 i channel 2 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb0 pin. primary ? ain3 i channel 3 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb1 pin. primary ? ain4 i channel 4 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb6 pin. primary ? ain5 i channel 5 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb7 pin. primary ? conparator cmp0p i non-inverting input for comparator0. this pin is used as the primary function of the pb4 pin. primary ? cmp0m i inverting input for comparator0. this pin is used as the primary function of the pb5 pin. primary ? cmp0out o output for comparator0. this pin is used as the quaternary function of the pa2 pin. quaternary ? cmp0out o output for comparator0. this pin is used as the quaternary function of the pb2 pin. quaternary ? cmp0out o output for comparator0. this pin is used as the quaternary function of the pb3 pin. quaternary ? cmp1p i non-inverting input for comparator1. this pin is used as the primary function of the pa1 pin. primary ? cmp1out o output for comparator1. this pin is used as the quaternary function of the pb0 pin. quaternary ? for testing test i/o input/output pin for testing. a pull-down resistor is internally connected. ? positive power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v pp ? power supply pin for flash rom ? ?
fedl610q101 -01 ml610q101/ML610Q102 10/21 ml610q101/ML610Q102 termination of unused pins table 3 shows methods of terminating the unused pins for ml610q101/ML610Q102. table 3 termination of unused pins pin recommended pin termination reset_n open test open pa0 to pa2 open pb0 to pb7 open v pp open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610q101 -01 ml610q101/ML610Q102 11/21 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 c ? 0.3 to + 7.0 v power supply voltage 2 v pp ta = 25 c ? 0.3 to + 9.5 v input voltage v in ta = 25 c ? 0.3 to v dd + 0.3 v output voltage v out ta = 25 c ? 0.3 to v dd + 0.3 v output current 1 i out1 ta = 25 c ? 12 to + 11 ma power dissipation pd ta = 25 c 0.5 mw storage temperature t stg ? ? 55 to + 150 c recommended operating conditions (v ss = 0v) parameter symbol condition range unit operating temperature t op ? ? 40 to +85 c operating voltage v dd ? 2.7 to 5.5 v operating frequency (cpu) f op v dd = 2.7v to 5.5v 30k to 8.4m hz operating conditions of flash memory (v ss =0v) rating parameter symbol condition min. typ. max. unit operating temperature t op at write/erase 0 D + 40 c v dd at write/erase 4.5 D 5.5 v operating voltage v pp at write/erase 7.7 D 8.3 rewrite counts c ep D D D 80 cycles data retention* 1 y dr D 10 D D years * 1 : however, please keep active time of the flash memory from exceeding ten years. vpp pin has internal pull-down resistor.
fedl610q101 -01 ml610q101/ML610Q102 12/21 dc characteristics (1/4) (v dd =2.7 to 5.5v, v ss =0v, ta= ? 40 to + 85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit low-speed rc oscillation frequency f rcl ta = 25 c 31 32.768 34 khz ta = 25 c typ. ? 1% 16.384 typ. + 1% ta = -10 to +85 c typ. -2% 16.384 typ. +2% pll oscillation frequency* 1 f pll ta = ? 40 to +85 c typ. ? 2.5% 16.384 typ. + 2.5% mhz reset pulse width t rst ? 100 D D reset noise elimination pulse width t nrst ? D D 0.4 s power-on reset activation power rise time t por ? D D 10 ms 1 * 1 : 1024 clock average. cpu clk is f pll /2 max. reset p rst reset_n reset_n pin reset vdd 0.9*v dd 0.3*v dd vdd 0.9*v dd 0.1*v dd t por power on reset p rst 0.3*v dd 0.3*v dd
fedl610q101 -01 ml610q101/ML610Q102 13/21 dc characteristics (2/4) (v dd =2.7 to 5.5v, v ss =0v, ta= ? 40 to + 85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ta=25 c , v dd =fall typ ? 3.0 % 2.85 typ +3.0 % v vls0f v dd =fall typ. ? 5.0 % 2.85 typ. + 5.0 % ta=25 c , v dd =rise typ. ? 3.0 % 2.92 typ. + 3.0 % v vls0r v dd =rise typ. ? 5.0 % 2.92 typ. + 5.0 % vls0=0 3.295 ta=25 c vls0=1 typ ? 3.0 % 3.625 typ +3.0 % vls0=0 3.295 vls judgment voltage v vls1 D vls0=1 typ ? 5.0 % 3.625 typ +5.0 % v 1 comparator0 in-phase input voltage range v cmr D 0.1 D v dd -1.5 v ta=25 c , v dd = 5.0v 10 20 30 comparator0 hysteresis v hysp v dd = 5.0v 5 20 35 comparator0 input offset voltage v cmof ta=25 c , v dd = 5.0v D D 7 ta=25 c -25 D 25 comparator reference- voltage error * 3 v cmref D -50 D 50 mv 4 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. ta=-40 to +85 c D 1 30 a supply current 2 idd2 cpu: in 32.768khz operating state.* 1 high-speed oscillation: stopped. ta=-40 to +85 c D 3.7 6 ma 1 * 1 : ltbc and wdt are operating ,and significant bits of blkcon0 to blkcon4 registers are all ?1?. * 2 : when the cpu operating rate is 100%. minimum instruction execution time: approx 0.122 s (at 8.192mhz system clock) * 3 :comparator input offset voltage is included.
fedl610q101 -01 ml610q101/ML610Q102 14/21 dc characteristics (3/4) (v dd =2.7 to 5.5v, v ss =0v, ta= ? 40 to + 85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit voh ioh1 = ? 3.0ma, v dd = 4.5v * 1 v dd ? 0.7 D D output voltage vol iol1 = + 8 . 5ma, v dd = 4.5v * 1 D D 0.6 v 2 iooh voh = v dd (in high-impedance state) D D +1 output leakage iool vol = v ss (in high-impedance state) ? 1 D D a 3 iih1 vih1 = v dd D D 1 input current 1 (reset_n) iil1 vil1 = v ss , v dd = 5.0v ? 650 ? 500 ? 350 iih1 vih1 = v dd = 5.0v 20 115 200 input current 1 (test) iil1 vil1 = v ss ? 1 D D iih2 vih2 = v dd = 5.0v (when pulled-down) 20 115 200 input current 2 (pa0-pa2) (pb0-pb7) iil2 vil2 = v ss , v dd =5.0v (when pulled-up) ? 200 ? 100 ? 20 a 4 * 1 : when the one terminal output state. dc characteristics (4/4) (v dd =2.7 to 5.5v, v ss =0v, ta= ? 40 to + 85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit vih1 ? 0.7 v dd D v dd input voltage 1 (reset_n) (test) (pa0 to pa2) (pb0,to pb7) vil1 ? 0 D 0.3 v dd v 2 input pin capacitance (pa0 to pa2) (pb0 to pb7) cin f = 10khz ta = 25 c D D 20 pf ?
fedl610q101 -01 ml610q101/ML610Q102 15/21 measuring circuits measuring circuit 1 measuring circuit 2 a v dd v ss c v 1 f c v input pins v dd v ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) (*1) current load v
fedl610q101 -01 ml610q101/ML610Q102 16/21 measuring circuit 3 measuring circuit 4 input pins a v dd v ss output pins *3: measured at the specified output pins. (*3) input pins a v dd v ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) (*1)
fedl610q101 -01 ml610q101/ML610Q102 17/21 ac characteristics (external interrupt) (v dd =2.7 to 5.5v, v ss =0v, ta= ? 40 to + 85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 2.5 x sysclk D 3.5 x sysclk s t nul pa0 to pa2, pb0 to pb1 (rising-edge interrupt) (falling-edge interrupt) p00 ,p01,pb0 ? pb2 (both-edge interrupt) t nul t nul pa0 to pa2, pb0 to pb1 pa0 to pa2, pb0 to pb1
fedl610q101 -01 ml610q101/ML610Q102 18/21 electrical characteristics of successive approximation type a/d converter (v dd =2.7 to 5.5v, v ss =0v, ta= ? 40 to + 85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit resolution n ? D D 10 bit integral non-linearity error inl r i Q 5k ? , hsclk = 8.192mhz ? 4 D + 4 differential non-linearity error dnl r i Q 5k ? , hsclk = 8.192mhz ? 3 D + 3 zero-scale error v off r i Q 5k ? , hsclk = 8.192mhz ? 4 D + 4 full-scale error fse r i Q 5k ? , hsclk = 8.192mhz ? 4 D + 4 lsb conversion time t conv ? D 102 D /ch : f pll /4 a v dd v ss analog input ? ri 5k ain0 to ain7 0.1 f + 10 f
fedl610q101 -01 ml610q101/ML610Q102 19/21 package dimensions (unit: mm) notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl610q101 -01 ml610q101/ML610Q102 20/21 revision history page document no. date previous edition current edition description fedl610q101-1 jan,23,2013 ? ? final edition 1
fedl610q101 -01 ml610q101/ML610Q102 21/21 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing la pis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd.

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